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» Dynamic Memory Design for Low Data-Retention Power
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ISCA
2007
IEEE
168views Hardware» more  ISCA 2007»
14 years 1 months ago
Limiting the power consumption of main memory
The peak power consumption of hardware components affects their power supply, packaging, and cooling requirements. When the peak power consumption is high, the hardware components...
Bruno Diniz, Dorgival Olavo Guedes Neto, Wagner Me...
APCCAS
2006
IEEE
206views Hardware» more  APCCAS 2006»
14 years 1 months ago
Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory
—A pre-comparison scheme is designed by using the NOR-type 10T content addressable memory (CAM) between the match line circuits and the pre-charging circuits. Thereby, several bi...
Po-Tsang Huang, Wei-Keng Chang, Wei Hwang
CASES
2006
ACM
14 years 1 months ago
FlashCache: a NAND flash memory file cache for low power web servers
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
Taeho Kgil, Trevor N. Mudge
ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
14 years 2 months ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
AVSS
2009
IEEE
13 years 5 months ago
Multimodal Abandoned/Removed Object Detection for Low Power Video Surveillance Systems
Low-cost and low-power video surveillance systems based on networks of wireless video sensors will enter soon the marketplace with the promise of flexibility, quick deployment an...
Michele Magno, Federico Tombari, Davide Brunelli, ...