1815 search results - page 53 / 363 » Dynamic Power Management Using Data Buffers |
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
The PowerPC 620TM microprocessor1 is the most recent and performance leading member of the PowerPCTM family. The 64-bit PowerPC 620 microprocessor employs a two-phase branch predi...
DSD
2004
IEEE
13 years 11 months ago
2004
IEEE
Tile-based rendering (also called chunk rendering or bucket rendering) is a promising technique for low-power, 3D graphics platforms. This technique decomposes a scene into smalle...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Line-rate data traffic monitoring in high-speed networks is essential for network management. To satisfy the line-rate requirement, one can leverage multi-core architectures to par...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
As the performance gap between processors and memory systems increases, the CPU spends more time stalled waiting for data from main memory. Critical long latency instructions, suc...
CIKM
2006
Springer
13 years 11 months ago
2006
Springer
By providing an integrated and optimized support for user-defined aggregates (UDAs), data stream management systems (DSMS) can achieve superior power and generality while preservi...