429 search results - page 12 / 86 » Dynamic Power Management of Multiprocessor Systems |
DSN
2007
IEEE
14 years 2 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
— Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of po...
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
This paper proposes DCC (Dynamic Cache Clustering), a novel distributed cache management scheme for large-scale chip multiprocessors. Using DCC, a per-core cache cluster is compri...
TCAD
2008
13 years 7 months ago
2008
Three-dimensional integration has the potential to improve the communication latency and integration density of chip-level multiprocessors (CMPs). However, the stacked highpower de...
SAC
2010
ACM
13 years 9 months ago
2010
ACM
Low-power and energy-efficient system implementations have become very important design issues to extend operation duration or cut power bills. To balance the energy consumption r...