Sciweavers

208 search results - page 37 / 42
» Dynamic Reconfiguration for Adaptive Multiversion Real-Time ...
Sort
View
ACSAC
2000
IEEE
13 years 12 months ago
Security Agility in Response to Intrusion Detection
Cooperative frameworks for intrusion detection and response exemplify a key area of today’s computer research: automating defenses against malicious attacks that increasingly ar...
M. Petkac, Lee Badger
IJCAI
1997
13 years 9 months ago
Evolvable Hardware for Generalized Neural Networks
This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to configure a scal...
Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani...
VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
14 years 8 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood
RTCSA
2005
IEEE
14 years 1 months ago
Extending Software Communications Architecture for QoS Support in SDR Signal Processing
The Software Communications Architecture (SCA) defined by Joint Tactical Radio Systems (JTRS) is the de facto standard middleware currently adopted by the Software Defined Radio (...
Jaesoo Lee, Jiyong Park, Seunghyun Han, Seongsoo H...
TVLSI
2008
164views more  TVLSI 2008»
13 years 7 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...