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119
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ICPP
2008
IEEE
15 years 9 months ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...
131
Voted
ASPDAC
2005
ACM
109views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Optimal module and voltage assignment for low-power
– Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study ...
Deming Chen, Jason Cong, Junjuan Xu
158
Voted
EMSOFT
2004
Springer
15 years 8 months ago
Practical PACE for embedded systems
In current embedded systems, one of the major concerns is energy conservation. The dynamic voltage-scheduling (DVS) framework, which involves dynamically adjusting the voltage and...
Ruibin Xu, Chenhai Xi, Rami G. Melhem, Daniel Moss...
ICSOC
2009
Springer
15 years 7 months ago
Message-Oriented Middleware with QoS Awareness
Publish/subscribe messaging is a fundamental mechanism for interconnecting disparate services and systems in the service-oriented computing architecture. The quality of services (Q...
Hao Yang, Minkyong Kim, Kyriakos Karenos, Fan Ye, ...
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
15 years 7 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee