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CONEXT
2007
ACM
14 years 26 days ago
On the cost of caching locator/ID mappings
Very recent activities in the IETF and in the Routing Research Group (RRG) of the IRTG focus on defining a new Internet architecture, in order to solve scalability issues related ...
Luigi Iannone, Olivier Bonaventure
FMCAD
2007
Springer
14 years 24 days ago
Circuit Level Verification of a High-Speed Toggle
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates verifying digital circuits using contin...
Chao Yan, Mark R. Greenstreet
DEBS
2009
ACM
14 years 24 days ago
MICS: an efficient content space representation model for publish/subscribe systems
One of the main challenges faced by content-based publish/subscribe systems is handling large amount of dynamic subscriptions and publications in a multidimensional content space....
Hojjat Jafarpour, Sharad Mehrotra, Nalini Venkatas...
ICCD
2007
IEEE
106views Hardware» more  ICCD 2007»
14 years 24 days ago
Transparent mode flip-flops for collapsible pipelines
Prior work has shown that collapsible pipelining techniques have the potential to significantly reduce clocking activity, which can consume up to 70% of the dynamic power in moder...
Eric L. Hill, Mikko H. Lipasti
ICCD
2007
IEEE
109views Hardware» more  ICCD 2007»
14 years 24 days ago
Improving cache efficiency via resizing + remapping
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...
Subramanian Ramaswamy, Sudhakar Yalamanchili