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113
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ICCD
2007
IEEE
99views Hardware» more  ICCD 2007»
15 years 6 months ago
Power reduction of chip multi-processors using shared resource control cooperating with DVFS
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Tak...
117
Voted
TCOM
2010
112views more  TCOM 2010»
15 years 1 months ago
On further reduction of complexity in tree pruning based sphere search
Abstract—In this letter, we propose an extension of the probabilistic tree pruning sphere decoding (PTP-SD) algorithm that provides further improvement of the computational compl...
Byonghyo Shim, Insung Kang
135
Voted
MICCAI
2004
Springer
16 years 3 months ago
A Data Clustering and Streamline Reduction Method for 3D MR Flow Vector Field Simplification
Abstract. With the increasing capability of MR imaging and Computational Fluid Dynamics (CFD) techniques, a significant amount of data related to the haemodynamics of the cardiovas...
Bernardo Silva Carmo, Yin-Heung Pauline Ng, Adam P...
118
Voted
VLSID
2008
IEEE
111views VLSI» more  VLSID 2008»
16 years 3 months ago
Power Reduction of Functional Units Considering Temperature and Process Variations
Continuous technology scaling has resulted in an increase in both, the power density as well as the variation in device dimensions (process variations) of the manufactured process...
Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj...
113
Voted
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
15 years 11 months ago
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction
Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduc...
Feng Gao, John P. Hayes