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ARVLSI
2001
IEEE
289views VLSI» more  ARVLSI 2001»
14 years 28 days ago
A High-Performance 64-bit Adder Implemented in Output Prediction Logic
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
Sheng Sun, Larry McMurchie, Carl Sechen
CONCUR
2006
Springer
13 years 11 months ago
Model Checking Quantified Computation Tree Logic
Propositional temporal logic is not suitable for expressing properties on the evolution of dynamically allocated entities over time. In particular, it is not possible to trace such...
Arend Rensink
ATAL
2010
Springer
13 years 10 months ago
A logical framework for prioritized goal change
Most previous logical accounts of goals do not deal with prioritized goals and goal dynamics properly. Many are restricted to achievement goals. In this paper, we develop a logica...
Shakil M. Khan, Yves Lespérance
DAC
2006
ACM
14 years 10 months ago
Predicate learning and selective theory deduction for a difference logic solver
Design and verification of systems at the Register-Transfer (RT) or behavioral level require the ability to reason at higher levels of abstraction. Difference logic consists of an...
Chao Wang, Aarti Gupta, Malay K. Ganai
WWW
2004
ACM
14 years 10 months ago
CTR-S: a logic for specifying contracts in semantic web services
A requirements analysis in the emerging field of Semantic Web Services (SWS) (see http://daml.org/services/swsl/requirements/) has identified four major areas of research: intelli...
Hasan Davulcu, Michael Kifer, I. V. Ramakrishnan