22 search results - page 4 / 5 » Dynamic partitioning of the cache hierarchy in shared data c... |
SIGARCH
2008
13 years 7 months ago
2008
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
SAMOS
2007
Springer
14 years 1 months ago
2007
Springer
— General purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies a...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
IPPS
1999
IEEE
13 years 11 months ago
1999
IEEE
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
CLUSTER
2008
IEEE
13 years 9 months ago
2008
IEEE
Efficient intra-node shared memory communication is important for High Performance Computing (HPC), especially with the emergence of multi-core architectures. As clusters continue ...