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» Dynamically Reconfigurable Vision-Chip Architecture
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ERSA
2004
130views Hardware» more  ERSA 2004»
14 years 9 days ago
Computing Lennard-Jones Potentials and Forces with Reconfigurable Hardware
Abstract-- Technological advances have made FPGAs an attractive platform for the acceleration of complex scientific applications. These applications demand high performance and hig...
Ronald Scrofano, Viktor K. Prasanna
CF
2005
ACM
14 years 26 days ago
Dynamic loop pipelining in data-driven architectures
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable computing platforms. Their use has provided performance improvements over micro...
João M. P. Cardoso
EUC
2004
Springer
14 years 4 months ago
Experimental Assessment of Scenario-Based Multithreading for Real-Time Object-Oriented Models: A Case Study with PBX Systems
This paper presents an experimental evaluation of our scenario-based multithreading for real-time object-oriented models by the use of a case study of a Private Branch eXchange (PB...
Saehwa Kim, Michael Buettner, Mark Hermeling, Seon...
ICSE
2009
IEEE-ACM
14 years 5 months ago
Improving the reliability of mobile software systems through continuous analysis and proactive reconfiguration
Most of the current software reliability analysis approaches are geared to traditional desktop software systems, which are relatively stable and static throughout their execution....
Sam Malek, Roshanak Roshandel, David Kilgore, Ibra...
IPPS
2000
IEEE
14 years 3 months ago
Reconfigurable Parallel Sorting and Load Balancing on a Beowulf Cluster: HeteroSort
HeteroSort load balances and sorts within static or dynamic networks using a conceptual torus mesh. We ported HeteroSort to a 16-node Beowulf cluster with a central switch architec...
Pamela Yang, Timothy M. Kunau, Bonnie Holte Bennet...