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INFOCOM
2009
IEEE
14 years 2 months ago
Power-Aware Speed Scaling in Processor Sharing Systems
—Energy use of computer communication systems has quickly become a vital design consideration. One effective method for reducing energy consumption is dynamic speed scaling, whic...
Adam Wierman, Lachlan L. H. Andrew, Ao Tang
CODES
2010
IEEE
13 years 5 months ago
Dynamic, non-linear cache architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
Garo Bournoutian, Alex Orailoglu
FPGA
2009
ACM
154views FPGA» more  FPGA 2009»
14 years 2 months ago
Synthesis of reconfigurable high-performance multicore systems
Reconfigurable high-performance computing systems (RHPC) have been attracting more and more attention over the past few years. RHPC systems are a promising solution for accelerati...
Jason Cong, Karthik Gururaj, Guoling Han
FPL
2008
Springer
86views Hardware» more  FPL 2008»
13 years 9 months ago
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors
In multi-context Dynamically Reconfigurable Processor Array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such c...
Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Ha...
TPDS
2010
93views more  TPDS 2010»
13 years 6 months ago
On the Interplay of Parallelization, Program Performance, and Energy Consumption
—This paper derives simple, yet fundamental formulas to describe the interplay between parallelism of an application, program performance, and energy consumption. Given the ratio...
Sangyeun Cho, Rami G. Melhem