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DELTA
2008
IEEE
14 years 2 months ago
Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications
The advances of CMOS technology towards 45 nm, the high costs of ASIC design, power limitations and fast changing application requirements have stimulated the usage of highly reco...
Hans G. Kerkhoff, Jarkko J. M. Huijts
DAGSTUHL
2006
13 years 9 months ago
Reliability-Aware Power Management Of Multi-Core Systems (MPSoCs)
Long-term reliability of processors in embedded systems is experiencing growing attention since decreasing feature sizes and increasing power consumption have a negative influence...
Klaus Waldschmidt, Jan Haase, Andreas Hofmann, Mar...
HPCA
1999
IEEE
13 years 12 months ago
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer proble...
David Brooks, Margaret Martonosi
DATE
2009
IEEE
131views Hardware» more  DATE 2009»
14 years 2 months ago
An event-guided approach to reducing voltage noise in processors
Abstract—Supply voltage fluctuations that result from inductive noise are increasingly troublesome in modern microprocessors. A voltage “emergency”, i.e., a swing beyond tol...
Meeta Sharma Gupta, Vijay Janapa Reddi, Glenn H. H...
CODES
2011
IEEE
12 years 7 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu