130 search results - page 16 / 26 » Dynamically Scheduling VLIW Instructions |
JUCS
2000
13 years 7 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
CGO
2003
IEEE
14 years 23 days ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
SIGOPSE
1998
ACM
13 years 11 months ago
1998
ACM
MMLite is a modular system architecture that is suitable for a wide variety of hardware and applications. The system provides a selection of object-based components that are dynam...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
EUROPAR
1998
Springer
13 years 11 months ago
1998
Springer
Instruction Balanced Time Slicing IBTS allows multiple parallel jobs to be scheduled in a manner akin to the well-known gang scheduling scheme in parallel computers. IBTS however a...