As the speed gap between CPU and I/O is getting wider and wider, I/O latency plays a more important role to the overall system performance than it used to be. Prefetching consecut...
Tsozen Yeh, Joseph Arul, Kuo-Hsin Tien, I-Fan Chen...
Dynamic voltage scaling (DVS) is an effective low-power design technique for embedded real-time systems. In recent years, many DVS algorithms have been proposed for reducing the e...
Woonseok Kim, Dongkun Shin, Han-Saem Yun, Jihong K...
We study the impact of user association policies on flow-level performance in interference limited wireless networks. Most research in this area has used static interference model...
Traditional software controlled data cache prefetching is often ineffective due to the lack of runtime cache miss and miss address information. To overcome this limitation, we imp...
Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobb...
Performance monitoring of large scale parallel computers creates a dilemma: we need to collect detailed information to find performance bottlenecks, yet collecting all this data ...