150 search results - page 24 / 30 » ECO timing optimization using spare cells |
152
Voted
SPAA
2005
ACM
15 years 9 months ago
2005
ACM
Switching cells in parallel is a common approach to build switches with very high external line rate and a large number of ports. A prime example is the parallel packet switch (in...
127
Voted
CCGRID
2008
IEEE
15 years 10 months ago
2008
IEEE
Understanding the potential and implications of asymmetric multi-core processors for cluster computing is necessary, as these processors are rapidly becoming mainstream components...
132
Voted
ISAAC
2007
Springer
15 years 9 months ago
2007
Springer
Abstract. We show how to represent sets in a linear space data structure such that expressions involving unions and intersections of sets can be computed in a worst-case efficient ...
117
Voted
WADS
2007
Springer
15 years 9 months ago
2007
Springer
In the faulty-memory RAM model, the content of memory cells can get corrupted at any time during the execution of an algorithm, and a constant number of uncorruptible registers are...
138
Voted
VLSID
2008
IEEE
15 years 10 months ago
2008
IEEE
It is well-known that varying architectural, technological and implementation aspects of embedded microprocessors, such as ARM, can produce widely differing performance and power ...