Sciweavers

40 search results - page 5 / 8
» Early Power Estimation for System-on-Chip Designs
Sort
View
PATMOS
2007
Springer
14 years 1 months ago
XEEMU: An Improved XScale Power Simulator
Energy efficiency is a top requirement in embedded system design. Understanding the complex issue of software power consumption in early design phases is of extreme importance to m...
Zoltán Herczeg, Ákos Kiss, Daniel Sc...
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 4 months ago
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques
— The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and highperformance mic...
Xiaoyao Liang, Kerem Turgay, David Brooks
ASPDAC
2000
ACM
102views Hardware» more  ASPDAC 2000»
13 years 12 months ago
A hybrid approach for core-based system-level power modeling
Reducing power consumption has become a key goal for systemon-a-chip (SOC) designs. Fast and accurate power estimation is needed early in the design process, since power reduction...
Tony Givargis, Frank Vahid, Jörg Henkel
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
14 years 1 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
ICDM
2007
IEEE
131views Data Mining» more  ICDM 2007»
13 years 11 months ago
Predicting and Optimizing Classifier Utility with the Power Law
When data collection is costly and/or takes a significant amount of time, an early prediction of the classifier performance is extremely important for the design of the data minin...
Mark Last