137 search results - page 24 / 28 » Effect of Event Orderings on Memory Requirement in Parallel ... |
IPPS
2010
IEEE
13 years 4 months ago
2010
IEEE
Quantum chemistry applications such as the General Atomic and Molecular Electronic Structure System (GAMESS) that can execute on a complex peta-scale parallel computing environment...
IPPS
2005
IEEE
14 years 9 days ago
2005
IEEE
— We consider a dense wireless sensor network where the radio transceivers of the sensor nodes are heavily duty-cycled in order to conserve energy. The chief purpose of the senso...
ISCA
1994
IEEE
13 years 10 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
ICASSP
2011
IEEE
12 years 10 months ago
2011
IEEE
Efficient operation of RF power amplifiers requires compensation strategies to mitigate nonlinear behavior. As bandwidth increases, memory effects become more pronounced, and Vo...
EGH
2010
Springer
13 years 4 months ago
2010
Springer
This paper proposes a massively parallel hardware architecture for efficient tracing of incoherent rays, e.g. for global illumination. The general approach is centered around hier...