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IPPS
2007
IEEE
14 years 1 months ago
Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
Colin J. Ihrig, Justin Stander, Alex K. Jones
ICCD
2008
IEEE
420views Hardware» more  ICCD 2008»
14 years 4 months ago
Frequency and voltage planning for multi-core processors under thermal constraints
— Clock frequency and transistor density increases have resulted in elevated chip temperatures. In order to meet temperature constraints while still exploiting the performance op...
Michael Kadin, Sherief Reda
CC
2010
Springer
190views System Software» more  CC 2010»
14 years 2 months ago
Is Reuse Distance Applicable to Data Locality Analysis on Chip Multiprocessors?
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...
Yunlian Jiang, Eddy Z. Zhang, Kai Tian, Xipeng She...
VLSID
2005
IEEE
149views VLSI» more  VLSID 2005»
14 years 8 months ago
ADOPT: An Approach to Activity Based Delay Optimization
: The direct result of shrinking devices is not only higher densities but also increased switching activity and thus higher device temperatures. The variation in temperature over t...
Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M....
EC
2000
241views ECommerce» more  EC 2000»
13 years 7 months ago
Cooperative Coevolution: An Architecture for Evolving Coadapted Subcomponents
To successfully apply evolutionary algorithms to the solution of increasingly complex problems, we must develop effective techniques for evolving solutions in the form of interact...
Mitchell A. Potter, Kenneth A. De Jong