377 search results - page 5 / 76 » Effective TARO Pattern Generation |
CORR
2011
Springer
13 years 2 months ago
2011
Springer
This paper investigates the impact of the changes of the characteristic polynomials and initial loadings, on behaviour of aliasing errors of parallel signature analyzer (Multi-Inp...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper presents 3LSSD, a novel, easilyautomatable approach for scan insertion and ATPG of asynchronous circuits. 3LSSD inserts scan latches only into global circuit feedback p...
ATS
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
DFT
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a procedure for Synthesis of LINear test pattern Generators called SLING. SLING can synthesize linear test pattern generators that satisfy constraints on area,...