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INFOCOM
2002
IEEE
14 years 1 months ago
Fair Scheduling and Buffer Management in Internet Routers
Abstract—Input buffered switch architecture has become attractive for implementing high performance routers and expanding use of the Internet sees an increasing need for quality ...
Nan Ni, Laxmi N. Bhuyan
ISCA
1995
IEEE
93views Hardware» more  ISCA 1995»
14 years 16 days ago
Optimizing Memory System Performance for Communication in Parallel Computers
Communicationin aparallel systemfrequently involvesmoving data from the memory of one node to the memory of another; this is the standard communication model employedin message pa...
Thomas Stricker, Thomas R. Gross
IQ
2007
13 years 10 months ago
Simulations Of Error Propagation For Prioritizing Data Accuracy Improvement Efforts
: Models of the association between input accuracy and output accuracy imply that, for any given application, the effect of input errors on the output error rate generally varies i...
Irit Askira Gelman
RTCSA
2007
IEEE
14 years 3 months ago
Scheduling Algorithms for I/O Blockings with a Multi-frame Task Model
A task that suspends itself to wait for an I/O completion or to wait for an event from another node in distributed environments is called an I/O blocking task. In conventional har...
Shan Ding, Hiroyuki Tomiyama, Hiroaki Takada
ICPR
2008
IEEE
14 years 3 months ago
Hybrid Layered Video Encoding for Mobile Internet-Based Computer Vision and Multimedia Applications
Mobile networked environments are typically resource constrained in terms of the available bandwidth and battery capacity on mobile devices. Realtime video applications entail the ...
Suchendra M. Bhandarkar, Siddhartha Chattopadhyay,...