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» Effects of on-chip inductance on power distribution grid
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WCE
2007
13 years 8 months ago
Power Flow Modelling of a Self-excited Induction Generator
—This paper presents power flow models of a self-excited induction generator. These models are used for steady-state power flow calculation in electric power systems in which a g...
Thanatchai Kulworawanichpong, P. Sangsarawut
GLVLSI
2006
IEEE
87views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Maximum effective distance of on-chip decoupling capacitors in power distribution grids
Mikhail Popovich, Eby G. Friedman, Michael Sotman,...
GLVLSI
2005
IEEE
144views VLSI» more  GLVLSI 2005»
14 years 1 months ago
On-chip power distribution grids with multiple supply voltages for high performance integrated circuits
—On-chip power distribution grids with multiple supply voltages are discussed in this paper. Two types of interdigitated and paired power distribution grids with multiple supply ...
Mikhail Popovich, Eby G. Friedman, Michael Sotman,...
ICCD
2006
IEEE
183views Hardware» more  ICCD 2006»
14 years 4 months ago
An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks
The placement of on-die decoupling capacitors (decap) between the power and ground supply grids has become a common practice in high performance processor designs. In this paper, ...
Sanjay Pant, David Blaauw
ISPD
2005
ACM
116views Hardware» more  ISPD 2005»
14 years 1 months ago
A fast algorithm for power grid design
This paper presents an efficient heuristic algorithm to design a power distribution network of a chip by employing a successive partitioning and grid refinement scheme. In an it...
Jaskirat Singh, Sachin S. Sapatnekar