56 search results - page 8 / 12 » Efficient Backtracking Instruction Schedulers |
IISWC
2008
IEEE
14 years 1 months ago
2008
IEEE
Heterogeneous multi-core processors are attractive for power efficient computing because of their ability to meet varied resource requirements of diverse applications in a workloa...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Speculative execution is execution of instructions before it is known whether these instructions should be executed. Compiler-based speculative execution has the potential to achi...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
Instruction scheduling methods based on the construction of state diagrams (or automata) have been used for architectures involving deeply pipelined function units. However, the s...
TCAD
2002
13 years 7 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
We address the design of algorithms for multicores that are oblivious to machine parameters. We propose HM, a multicore model consisting of a parallel shared-memory machine with hi...