An instruction-level energy model for embedded VLIW architectures

In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power consumption information during either an instruction-level simulation or power-oriented scheduling at compile time. The analytical model takes into account several software-level parameters (such as instruction ordering, pipeline stall probability, and instruction cache miss probability) as well as microarchitectural-level ones (such as pipeline stage power consumption per instruction) providing an efficient pipeline-aware instruction-level power estimation, whose accuracy is very close to those given by RT or gate-level simulations. The problem of instruction-level power characterization of a -issue VLIW processor is ( 2 ) where is the number of operations in the ISA and is the number of parallel instructions composing the very long instruction. One of the advantages of the proposed model consists of reducin...

• Type: Journal
• Year: 2002
• Where: TCAD
• Authors: Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
• Keywords: Instruction, Instruction-level Power Estimation, Power Consumption, TCAD 2002