1156 search results - page 186 / 232 » Efficient Barriers for Distributed Shared Memory Computers |
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
ICDCS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--The networked application environment has motivated the development of multitasking operating systems for sensor networks and other low-power electronic devices, but thei...
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...
IEEEPACT
1998
IEEE
13 years 12 months ago
1998
IEEE
Register coalescing is used, as part of register allocation, to reduce the number of register copies. Developing efficient register coalescing heuristics is particularly important ...
CCGRID
2010
IEEE
13 years 8 months ago
2010
IEEE
Map-reduce framework has received a significant attention and is being used for programming both large-scale clusters and multi-core systems. While the high productivity aspect of ...