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ISSS
1997
IEEE
102views Hardware» more  ISSS 1997»
14 years 2 days ago
An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy
This paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model along with logical propositions is used to create an ...
Catherine H. Gebotys
EUROPAR
2010
Springer
13 years 8 months ago
Source-to-Source Optimization of CUDA C for GPU Accelerated Cardiac Cell Modeling
Large and complex systems of ordinary differential equations (ODEs) arise in diverse areas of science and engineering, and pose special challenges on a streaming processor owing to...
Fred V. Lionetti, Andrew D. McCulloch, Scott B. Ba...
CODES
2010
IEEE
13 years 5 months ago
Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming
The last years have shown that there is no way to disregard the advantages provided by multiprocessor System-on-Chip (MPSoC) architectures in the embedded systems domain. Using mu...
Daniel Cordes, Peter Marwedel, Arindam Mallik
HPCC
2007
Springer
13 years 11 months ago
Checkpointing Aided Parallel Execution Model and Analysis
Abstract. Checkpointing techniques are usually used to secure the execution of sequential and parallel programs. However, they can also be used in order to generate automatically a...
Laura Mereuta, Éric Renault
OSDI
1994
ACM
13 years 9 months ago
Distributed Filaments: Efficient Fine-Grain Parallelism on a Cluster of Workstations
A fine-grain parallel program is one in which processes are typically small, ranging from a few to a few hundred instructions. Fine-grain parallelism arises naturally in many situ...
Vincent W. Freeh, David K. Lowenthal, Gregory R. A...