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» Efficient Design Error Correction of Digital Circuits
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DFT
2000
IEEE
105views VLSI» more  DFT 2000»
14 years 1 months ago
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits
Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: dom...
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang...
VLSID
2005
IEEE
126views VLSI» more  VLSID 2005»
14 years 9 months ago
Exact Analytical Equations for Predicting Nonlinear Phase Errors and Jitter in Ring Oscillators
In this paper, we present a simple analytical equation for capturing phase errors in 3-stage ring oscillators. The model, based on a simple but useful idealization of the ring osc...
Jaijeet S. Roychowdhury
JCDL
2010
ACM
143views Education» more  JCDL 2010»
14 years 1 months ago
ProcessTron: efficient semi-automated markup generation for scientific documents
Digitizing legacy documents and marking them up with XML is important for many scientific domains. However, creating comprehensive semantic markup of high quality is challenging. ...
Guido Sautter, Klemens Böhm, Conny Kühne...
VLSISP
2002
103views more  VLSISP 2002»
13 years 8 months ago
A New Class of Efficient Block-Iterative Interference Cancellation Techniques for Digital Communication Receivers
A new and efficient class of nonlinear receivers is introduced for digital communication systems. These "iterated-decision" receivers use optimized multipass algorithms t...
Albert M. Chan, Gregory W. Wornell
INFOCOM
2009
IEEE
14 years 3 months ago
Circuits/Cutsets Duality and a Unified Algorithmic Framework for Survivable Logical Topology Design in IP-over-WDM Optical Netwo
: Given a logical topology and a physical topology , the survivable logical topology design problem in an IP-overWDM optical network is to map the logical links into lightpaths in ...
Krishnaiyan Thulasiraman, Muhammad S. Javed, Guoli...