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IPPS
1999
IEEE
13 years 11 months ago
FPGA Implementation of Modular Exponentiation
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...
Alexander Tiountchik, Elena Trichina
ERSA
2010
199views Hardware» more  ERSA 2010»
13 years 5 months ago
Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
Russell Tessier, Salma Mirza, J. Blair Perot
FPL
2000
Springer
124views Hardware» more  FPL 2000»
13 years 11 months ago
Balancing Logic Utilization and Area Efficiency in FPGAs
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
Russell Tessier, Heather Giza
AFRICACRYPT
2009
Springer
13 years 5 months ago
Efficient Acceleration of Asymmetric Cryptography on Graphics Hardware
Graphics processing units (GPU) are increasingly being used for general purpose computing. We present implementations of large integer modular exponentiation, the core of public-ke...
Owen Harrison, John Waldron
PROCEDIA
2010
138views more  PROCEDIA 2010»
13 years 2 months ago
Using the reconfigurable massively parallel architecture COPACOBANA 5000 for applications in bioinformatics
Currently several computational problems require high processing power to handle huge amounts of data, although underlying core algorithms appear to be rather simple. Especially i...
Lars Wienbrandt, Stefan Baumgart, Jost Bissel, Car...