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TVLSI
2008
121views more  TVLSI 2008»
13 years 7 months ago
Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores
Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-p...
Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna
IPPS
2007
IEEE
14 years 1 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
JIRS
2007
108views more  JIRS 2007»
13 years 7 months ago
Task-based Hardware Reconfiguration in Mobile Robots Using FPGAs
This paper presents a methodology for the realization of intelligent, task-based reconfiguration of the computational hardware for mobile robot applications. Task requirements are ...
Sesh Commuri, V. Tadigotla, L. Sliger
FPL
2006
Springer
140views Hardware» more  FPL 2006»
13 years 11 months ago
Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs
FPGAs have reached densities that can implement floatingpoint applications, but floating-point operations still require a large amount of FPGA resources. One major component of IE...
Michael J. Beauchamp, Scott Hauck, Keith D. Underw...
VLSISP
2010
119views more  VLSISP 2010»
13 years 2 months ago
Hardware Acceleration of HMMER on FPGAs
We propose a new parallelization scheme for the hmmsearch function of the HMMER software, in order to target FPGA technology. hmmsearch is a very compute intensive software for bio...
Steven Derrien, Patrice Quinton