Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores

Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-performance floating-point arithmetic. To achieve high clock rates, floating-point cores for FPGAs must be deeply pipelined. This deep pipelining makes it difficult to reuse the same floating-point core for a series of dependent computations. However, floating-point cores use a great deal of area, so it is important to use as few of them in an architecture as possible. In this paper, we describe area-efficient architectures and algorithms for arithmetic expression evaluation. Such expression evaluation is necessary in applications from a wide variety of fields, including scientific computing and cognition. The proposed designs effectively hide the pipeline latency of the floating-point cores and use at most two floating-point cores for each type of operator in the expression. While best-suited for particular c...

• Type: Journal
• Year: 2008
• Where: TVLSI
• Authors: Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna
• Keywords: Expression Evaluation, Floating-point, Floating-point Cores, TVLSI 2008