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SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
14 years 1 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
IJNSEC
2010
247views more  IJNSEC 2010»
13 years 2 months ago
Hardware Implementation of Efficient Modified Karatsuba Multiplier Used in Elliptic Curves
The efficiency of the core Galois field arithmetic improves the performance of elliptic curve based public key cryptosystem implementation. This paper describes the design and imp...
Sameh M. Shohdy, Ashraf El-Sisi, Nabil A. Ismail
CODES
2006
IEEE
13 years 11 months ago
Increasing hardware efficiency with multifunction loop accelerators
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
BMCBI
2008
211views more  BMCBI 2008»
13 years 7 months ago
CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment
Background: Searching for similarities in protein and DNA databases has become a routine procedure in Molecular Biology. The Smith-Waterman algorithm has been available for more t...
Svetlin Manavski, Giorgio Valle
ACIVS
2008
Springer
13 years 9 months ago
An Efficient Hardware Architecture without Line Memories for Morphological Image Processing
In this paper, we present a novel hardware architecture to achieve erosion and dilation with a large structuring element. We are proposing a modification of HGW algorithm with a bl...
Christophe Clienti, Michel Bilodeau, Serge Beucher