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ASPDAC
2008
ACM
115views Hardware» more  ASPDAC 2008»
15 years 6 months ago
An optimal algorithm for sizing sequential circuits for industrial library based designs
In this paper, we propose an optimal gate sizing and clock skew optimization algorithm for globally sizing synchronous sequential circuits. The number of constraints and variables ...
Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Che...
ASPDAC
2008
ACM
145views Hardware» more  ASPDAC 2008»
15 years 6 months ago
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
- We present a topology synthesis method for high performance System-on-Chip (SoC) design. Our method provides an optimal topology of on-chip communication network for the given ba...
Minje Jun, Sungjoo Yoo, Eui-Young Chung
ASPDAC
2008
ACM
169views Hardware» more  ASPDAC 2008»
15 years 6 months ago
Buffered clock tree synthesis for 3D ICs under thermal variations
In this paper, we study the buffered clock tree synthesis problem under thermal variations for 3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides...
Jacob R. Minz, Xin Zhao, Sung Kyu Lim
ASPDAC
2008
ACM
174views Hardware» more  ASPDAC 2008»
15 years 6 months ago
Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty
In modern circuit design, it is difficult to provide reliable parametric yield prediction since the real distribution of process data is hard to measure. Most existing approaches ...
Jin Sun, Yue Huang, Jun Li, Janet Meiling Wang
ASPDAC
2008
ACM
124views Hardware» more  ASPDAC 2008»
15 years 6 months ago
MaizeRouter: Engineering an effective global router
In this paper, we present the complete design and architectural details of MAIZEROUTER. MAIZEROUTER reflects a significant leap in progress over existing publicly available routing...
Michael D. Moffitt