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DAC
2007
ACM
16 years 5 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
2007
ACM
16 years 5 months ago
Chip Multi-Processor Generator
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
Alex Solomatnikov, Amin Firoozshahian, Wajahat Qad...
DAC
2000
ACM
16 years 5 months ago
Power analysis of embedded operating systems
The increasing complexity and software content of embedded systems has led to the common use of sophisticated system software that helps applications use the underlying hardware r...
Robert P. Dick, Ganesh Lakshminarayana, Anand Ragh...
DAC
2003
ACM
16 years 5 months ago
Multilevel global placement with retiming
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
Jason Cong, Xin Yuan
DAC
2003
ACM
16 years 5 months ago
Coverage directed test generation for functional verification using bayesian networks
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
Shai Fine, Avi Ziv