2620 search results - page 487 / 524 » Efficient Hardware Voxelization |
109
Voted
MICRO
2010
IEEE
15 years 1 months ago
2010
IEEE
Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key...
127
Voted
MICRO
2010
IEEE
15 years 1 months ago
2010
IEEE
The ever-increasing importance of main memory latency and bandwidth is pushing CMPs towards caches with higher capacity and associativity. Associativity is typically improved by in...
123
Voted
MICRO
2010
IEEE
15 years 1 months ago
2010
IEEE
Current trends signal an imminent crisis in the simulation of future CMPs (Chip MultiProcessors). Future micro-architectures will offer more and more thread contexts to execute pa...
138
Voted
ICCAD
2009
IEEE
15 years 1 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
146
Voted
ICCAD
2009
IEEE
15 years 1 months ago
2009
IEEE
In a behavioral synthesis system, a typical approach used to guide the scheduler is to impose hard constraints on the relative timing between operations considering performance, a...