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» Efficient Hardware for Antialiasing Coverage Mask Generation
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ATS
1996
IEEE
117views Hardware» more  ATS 1996»
13 years 12 months ago
Hierarchical Test Generation with Built-In Fault Diagnosis
A hierarchical test generation method is presented that uses the inherent hierarchical structure of the circuit under test and takes fault diagnosability into account right from t...
Dirk Stroobandt, Jan Van Campenhout
ATS
2002
IEEE
108views Hardware» more  ATS 2002»
14 years 20 days ago
Fault Set Partition for Efficient Width Compression
In this paper, we present a technique for reducing the test length of counter-based pseudo-exhaustive built-in self-testing (BIST) based on width compression method. More formally...
Emil Gizdarski, Hideo Fujiwara
ATS
2004
IEEE
87views Hardware» more  ATS 2004»
13 years 11 months ago
Low Power BIST with Smoother and Scan-Chain Reorder
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu
ETS
2006
IEEE
122views Hardware» more  ETS 2006»
13 years 11 months ago
Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics
Online repair through reconfiguration is a particularly advantageous approach in the nanoelectronic environment since reconfigurability is naturally supported by the devices. Howe...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
ASPDAC
2006
ACM
122views Hardware» more  ASPDAC 2006»
14 years 1 months ago
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, ...