Sciweavers

255 search results - page 45 / 51
» Efficient Optimistic Parallel Simulations Using Reverse Comp...
Sort
View
ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
13 years 11 months ago
Tempest and Typhoon: User-Level Shared Memory
Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, parallel programming languages. Today's machines ...
Steven K. Reinhardt, James R. Larus, David A. Wood
SI3D
1995
ACM
13 years 11 months ago
The Sort-First Rendering Architecture for High-Performance Graphics
Interactive graphics applications have long been challenging graphics system designers by demanding machines that can provide ever increasing polygon rendering performance. Anothe...
Carl Mueller
ICPP
2006
IEEE
14 years 1 months ago
Data Sharing Pattern Aware Scheduling on Grids
These days an increasing number of applications, especially in science and engineering, are dealing with a massive amount of data; hence they are dataintensive. Bioinformatics, da...
Young Choon Lee, Albert Y. Zomaya
ICPP
2008
IEEE
14 years 1 months ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...
ICPPW
2009
IEEE
13 years 5 months ago
Improvement of Messages Delivery Time on Vehicular Delay-Tolerant Networks
Vehicular Delay-Tolerant Networks (VDTNs) are an application of the Delay-Tolerant Network (DTN) concept, where the movement of vehicles and their message relaying service is used ...
Vasco Nuno da Gama de Jesus Soares, Joel Jos&eacut...