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ISVLSI
2006
IEEE
149views VLSI» more  ISVLSI 2006»
14 years 1 months ago
Defect-Aware Design Paradigm for Reconfigurable Architectures
With advances in process technology, the feature sizes are decreasing, which leads to higher defect densities. More sophisticated techniques, at increased costs are required to av...
Rahul Jain, Anindita Mukherjee, Kolin Paul
SIGARCH
2010
89views more  SIGARCH 2010»
13 years 2 months ago
Efficient reconfigurable design for pricing asian options
Arithmetic Asian options are financial derivatives which have the feature of path-dependency: they depend on the entire price path of the underlying asset, rather than just the in...
Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, ...
IJES
2006
72views more  IJES 2006»
13 years 7 months ago
Non-contiguous linear placement for reconfigurable fabrics
: We present efficient solutions for the non-contiguous linear placement of data-paths for reconfigurable fabrics. A strip-based architecture is assumed for the reconfigurable fabr...
Cristinel Ababei, Kia Bazargan
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
14 years 23 days ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar
ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
14 years 29 days ago
An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays
—This paper presents a memory-conscious mapping methodology of computational intensive applications on coarse-grain reconfigurable arrays. By exploiting the inherent abundant amo...
Michalis D. Galanis, Gregory Dimitroulakos, Consta...