130 search results - page 2 / 26 » Efficient Selection of Vector Instructions Using Dynamic Pro... |
CASES
2008
ACM
13 years 9 months ago
2008
ACM
Automatic vectorization of programs for partitioned-ALU SIMD (Single Instruction Multiple Data) processors has been difficult because of not only data dependency issues but also n...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
A new dynamic vector approach for the selection and management of the configuration of a reconfigurable superscalar processor is proposed. This new method improves on previous wor...
MICRO
1998
IEEE
13 years 11 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
ISCA
2002
IEEE
14 years 12 days ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
RTAS
1996
IEEE
13 years 11 months ago
1996
IEEE
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...