391 search results - page 51 / 79 » Efficient Self-Reconfigurable Implementations Using On-chip ... |
HIPC
2007
Springer
14 years 1 months ago
2007
Springer
: The Cell is a heterogeneous multi-core processor, which has eight co-processors, called SPEs. The SPEs can access a common shared main memory through DMA, and each SPE can direct...
RTCSA
2005
IEEE
14 years 1 months ago
2005
IEEE
Embedded systems are usually resource limited in terms of processing power, memory, and power consumption, thus embedded TCP/IP should be designed to make the best use of limited ...
ICASSP
2010
IEEE
13 years 8 months ago
2010
IEEE
Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient managem...
TCOM
2010
13 years 2 months ago
2010
In this paper, we propose a new implementation of the Extended Min-Sum (EMS) decoder for non-binary LDPC codes. A particularity of the new algorithm is that it takes into accounts...
VLSISP
2008
13 years 7 months ago
2008
Digital signal processing (DSP) applications involve processing long streams of input data. It is important to take into account this form of processing when implementing embedded ...