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IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
15 years 7 months ago
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
PAMI
2002
164views more  PAMI 2002»
15 years 2 months ago
Efficient Dilation, Erosion, Opening, and Closing Algorithms
We propose an efficient and deterministic algorithm for computing the one-dimensional dilation and erosion (max and min) sliding window filters. For a p-element sliding window, our...
Joseph Gil, Ron Kimmel
INFOCOM
2002
IEEE
15 years 7 months ago
Efficient Dissemination of Personalized Information Using Content-Based Multicast
There has been a surge of interest in the delivery of personalized information to users (e.g. personalized stocks or travel information), particularly as mobile users with limited ...
Rahul Shah, Ravi Jain, Farooq Anjum
MICRO
1997
IEEE
139views Hardware» more  MICRO 1997»
15 years 6 months ago
The Filter Cache: An Energy Efficient Memory Structure
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
Johnson Kin, Munish Gupta, William H. Mangione-Smi...
ARCS
2006
Springer
15 years 6 months ago
Efficient System-on-Chip Energy Management with a Segmented Bloom Filter
As applications tend to grow more complex and use more memory, the demand for cache space increases. Thus embedded processors are inclined to use larger caches. Predicting a miss i...
Mrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien...