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» Efficient assertion based verification using TLM
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TSE
2010
125views more  TSE 2010»
13 years 8 months ago
Engineering a Sound Assertion Semantics for the Verifying Compiler
—The Verifying Compiler (VC) project is a core component of the Dependable Systems Evolution Grand Challenge. The VC offers the promise of automatically proving that a program or...
Patrice Chalin
JUCS
2006
121views more  JUCS 2006»
13 years 9 months ago
On-line Monitoring of Metric Temporal Logic with Time-Series Constraints Using Alternating Finite Automata
: In this paper we describe a technique for monitoring and checking temporal logic assertions augmented with real-time and time-series constraints, or Metric Temporal Logic Series ...
Doron Drusinsky
TODAES
2008
115views more  TODAES 2008»
13 years 9 months ago
Automata-based assertion-checker synthesis of PSL properties
Abstract-- Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We ...
Marc Boule, Zeljko Zilic
RSP
2006
IEEE
125views Control Systems» more  RSP 2006»
14 years 3 months ago
Creation and Validation of Embedded Assertion Statecharts
This paper addresses the need to integrate formal assertions into the modeling, implementation, and testing of statechart based designs. The paper describes an iterative process f...
Doron Drusinsky, Man-tak Shing, Kadir Alpaslan Dem...
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
14 years 1 months ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...