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» Efficient checker processor design
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VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
14 years 7 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...
SIGMOD
2007
ACM
179views Database» more  SIGMOD 2007»
14 years 7 months ago
How to barter bits for chronons: compression and bandwidth trade offs for database scans
Two trends are converging to make the CPU cost of a table scan a more important component of database performance. First, table scans are becoming a larger fraction of the query p...
Allison L. Holloway, Vijayshankar Raman, Garret Sw...
SIGMOD
2002
ACM
236views Database» more  SIGMOD 2002»
14 years 7 months ago
The Cougar Approach to In-Network Query Processing in Sensor Networks
The widespread distribution and availability of smallscale sensors, actuators, and embedded processors is transforming the physical world into a computing platform. One such examp...
Yong Yao, Johannes Gehrke
PODS
2002
ACM
168views Database» more  PODS 2002»
14 years 7 months ago
Conjunctive Selection Conditions in Main Memory
We consider the fundamental operation of applying a conjunction of selection conditions to a set of records. With large main memories available cheaply, systems may choose to keep...
Kenneth A. Ross
PPOPP
2006
ACM
14 years 1 months ago
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hu...