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FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
14 years 4 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
AOSD
2008
ACM
13 years 9 months ago
AJANA: a general framework for source-code-level interprocedural dataflow analysis of AspectJ software
Aspect-oriented software presents new challenges for the designers of static analyses. Our work aims to establish systematic foundations for dataflow analysis of AspectJ software....
Guoqing Xu, Atanas Rountev
CVPR
2007
IEEE
14 years 9 months ago
Optimizing Binary MRFs via Extended Roof Duality
Many computer vision applications rely on the efficient optimization of challenging, so-called non-submodular, binary pairwise MRFs. A promising graph cut based approach for optim...
Carsten Rother, Vladimir Kolmogorov, Victor S. Lem...
DATE
1999
IEEE
194views Hardware» more  DATE 1999»
13 years 11 months ago
CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
Bharat P. Dav
CL
2008
Springer
13 years 7 months ago
Automatic synthesis and verification of real-time embedded software for mobile and ubiquitous systems
Currently available application frameworks that target the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for m...
Pao-Ann Hsiung, Shang-Wei Lin