555 search results - page 18 / 111 » Efficient event-driven simulation of parallel processor arch... |
IEEEHPCS
2010
2010
Novel performance optimization of large-scale discrete-event simulation on the Cell Broadband Engine
13 years 8 months ago
This paper presents a computing technique for efficient parallel simulation of large-scale discrete-event models on the IBM Cell Broadband Engine (CBE), which has one Power Proces...
IPPS
2003
IEEE
14 years 3 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
IPPS
2007
IEEE
14 years 4 months ago
2007
IEEE
1 Multi-paradigm, multi-threaded and multi-core computing devices available today provide several orders of magnitude performance improvement over mainstream microprocessors. These...
ICPP
2008
IEEE
14 years 4 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
INFORMATICALT
2006
13 years 10 months ago
2006
The paper describes the development and performance of parallel algorithms for the discrete element method (DEM) software. Spatial domain decomposition strategy and message passing...