120 search results - page 17 / 24 » Efficient hardware code generation for FPGAs |
FPL
2006
Springer
13 years 11 months ago
2006
Springer
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
ITC
1993
IEEE
13 years 11 months ago
1993
IEEE
ÐPseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detecta...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper we propose a dynamic code overlay technique of synchronous data-flow (SDF) –modeled program for low-end embedded systems which lack MMUsupport. With this technique...
ICIP
2009
IEEE
14 years 8 months ago
2009
IEEE
In implementing an efficient block coder for JPEG2000, the memories required for storing the state variables dominate the hardware cost of a block coder. In this paper, we propose...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
The principal objectives of next generation wireless communication are the delivery of higher data rate services including video, audio, data and voice signals with worldwide comp...