120 search results - page 20 / 24 » Efficient hardware code generation for FPGAs |
FPL
2010
Springer
13 years 5 months ago
2010
Springer
We demonstrate how Field Programmable Gate Arrays (FPGAs) may be used to address the computing challenges associated with assembling genome sequences from recent ultra-high-through...
FCCM
2011
IEEE
12 years 11 months ago
2011
IEEE
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
SAC
2010
ACM
13 years 9 months ago
2010
ACM
The control flow of common processors does not match the specific needs of reactive systems. Key issues for these systems are preemption and concurrency, combined with timing pred...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software ? e.g., into sequent...
CCL
1994
Springer
13 years 11 months ago
1994
Springer
Abstract: This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with ef...