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» Efficient memory simulation in SimICS
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HPCA
2005
IEEE
14 years 8 months ago
A Unified Compressed Memory Hierarchy
The memory system's large and growing contribution to system performance motivates more aggressive approaches to improving its efficiency. We propose and analyze a memory hie...
Erik G. Hallnor, Steven K. Reinhardt
IPPS
2009
IEEE
14 years 2 months ago
Core-aware memory access scheduling schemes
Multi-core processors have changed the conventional hardware structure and require a rethinking of system scheduling and resource management to utilize them efficiently. However, ...
Zhibin Fang, Xian-He Sun, Yong Chen, Surendra Byna
ICCD
1999
IEEE
122views Hardware» more  ICCD 1999»
13 years 12 months ago
Design and Evaluation of a Selective Compressed Memory System
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
ICC
2007
IEEE
138views Communications» more  ICC 2007»
14 years 1 months ago
Scalable Router Memory Architecture Based on Inter-leaved DRAM: Analysis and Numerical Studies
1  Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitabl...
Feng Wang, Mounir Hamdi
CORR
2010
Springer
133views Education» more  CORR 2010»
13 years 7 months ago
Computational efficiency of fractional diffusion using adaptive time step memory
Abstract: Numerical solutions to fractional differential equations can be extremely computationally intensive due to the effect of non-local derivatives in which all previous time ...
Brian P. Sprouse, Christopher L. MacDonald, Gabrie...