258 search results - page 14 / 52 » Efficient memory simulation in SimICS |
ICDE
1999
IEEE
14 years 9 months ago
1999
IEEE
In this paper we present an online method for managing a goaloriented buffer partitioning in the distributed memory of a network of workstations. Our algorithm implements a feedba...
IPPS
2000
IEEE
14 years 16 hour ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...
CCECE
2009
IEEE
14 years 2 months ago
2009
IEEE
— Most of the existing video streaming systems employ the worst case analysis in application layer buffer size dimensioning. Even though the worst case buffer size dimensioning p...
EUROPAR
2007
Springer
13 years 11 months ago
2007
Springer
To understand the principles of information processing in the brain, we depend on models with more than 105 neurons and 109 connections. These networks can be described as graphs o...