ISQED 2009 - PDF Preprint Papers

ISQED 2009 International Symposium on Quality Electronic Design

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ISQED
2009
IEEE

328views Hardware» more ISQED 2009»

VLSI architectures of perceptual based video watermarking for real-time copyright protection

14 years 6 months ago

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For effective digital rights management (DRM) of multimedia in the framework of embedded systems, both watermarking and cryptography are necessary. In this paper, we present a wat...

Saraju P. Mohanty, Elias Kougianos, Wei Cai, Manis...

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Id	Views	Title	Status

1	328	VLSI architectures of perceptual based video watermarking for real-time copyright protection	claim
2	196	A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme	claim
3	187	An efficient current-based logic cell model for crosstalk delay analysis	claim
4	137	Active decap design considerations for optimal supply noise reduction	claim
5	136	NBTI aware workload balancing in multi-core systems	claim
6	135	Simultaneous test pattern compaction, ordering and X-filling for testing power reduction	claim
7	133	A novel ACO-based pattern generation for peak power estimation in VLSI circuits	claim
8	126	New subthreshold concepts in 65nm CMOS technology	claim
9	126	Robust differential asynchronous nanoelectronic circuits	claim
10	124	Revisiting the linear programming framework for leakage power vs. performance optimization	claim
11	117	Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution	claim
12	115	TuneLogic: Post-silicon tuning of dual-Vdd designs	claim
13	112	Estimation and optimization of reliability of noisy digital circuits	claim
14	111	Efficient statistical analysis of read timing failures in SRAM circuits	claim
15	109	Variation-tolerant hierarchical voltage monitoring circuit for soft error detection	claim
16	106	Design and application of multimodal power gating structures	claim
17	103	A systematic approach to modeling and analysis of transient faults in logic circuits	claim
18	99	Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences	claim
19	94	Simultaneous buffer and interlayer via planning for 3D floorplanning	claim
20	91	Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments	claim
21	86	Uncriticality-directed scheduling for tackling variation and power challenges	claim
22	70	On-chip transistor characterization arrays with digital interfaces for variability characterization	claim
23	70	Place and route considerations for voltage interpolated designs	claim
24	69	Parametric analysis to determine accurate interconnect extraction corners for design performance	claim

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