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» Efficient reachability checking using sequential SAT
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FORMATS
2004
Springer
14 years 3 months ago
Bounded Model Checking for Region Automata
For successful software verification, model checkers must be capable of handling a large number of program variables. Traditional, BDD-based model checking is deficient in this reg...
Fang Yu, Bow-Yaw Wang, Yao-Wen Huang
FMCAD
2000
Springer
14 years 1 months ago
Scalable Distributed On-the-Fly Symbolic Model Checking
Abstract. This paper presents a scalable method for parallel symbolic on-the-fly model checking in a distributed memory environment. Our method combines a scheme for on-the-fly mod...
Shoham Ben-David, Tamir Heyman, Orna Grumberg, Ass...
DAC
2001
ACM
14 years 10 months ago
Circuit-based Boolean Reasoning
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...
Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi
ATVA
2004
Springer
138views Hardware» more  ATVA 2004»
14 years 1 months ago
Providing Automated Verification in HOL Using MDGs
While model checking suffers from the state space explosion problem, theorem proving is quite tedious and impractical for verifying complex designs. In this work, we present a veri...
Tarek Mhamdi, Sofiène Tahar
CAV
2008
Springer
108views Hardware» more  CAV 2008»
13 years 11 months ago
Reducing Concurrent Analysis Under a Context Bound to Sequential Analysis
This paper addresses the analysis of concurrent programs with shared memory. Such an analysis is undecidable in the presence of multiple procedures. One approach used in recent wor...
Akash Lal, Thomas W. Reps