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» Efficient reachability checking using sequential SAT
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ICCAD
2002
IEEE
146views Hardware» more  ICCAD 2002»
14 years 7 months ago
Conflict driven learning in a quantified Boolean Satisfiability solver
Within the verification community, there has been a recent increase in interest in Quantified Boolean Formula evaluation (QBF) as many interesting sequential circuit verification ...
Lintao Zhang, Sharad Malik
TABLEAUX
1998
Springer
14 years 3 months ago
Model Checking: Historical Perspective and Example (Extended Abstract)
ple (Extended Abstract) Edmund M. Clarke and Sergey Berezin Carnegie Mellon University -- USA Model checking is an automatic verification technique for finite state concurrent syst...
Edmund M. Clarke, Sergey Berezin
AAAI
2008
14 years 4 hour ago
Querying Sequential and Concurrent Horn Transaction Logic Programs Using Tabling Techniques
In this poster we describe the tabling techniques for Sequential and Concurrent Horn Transaction Logic. Horn Transaction Logic is an extension of classical logic programming with ...
Paul Fodor
ASPLOS
2008
ACM
14 years 26 days ago
Parallelizing security checks on commodity hardware
Speck1 is a system that accelerates powerful security checks on commodity hardware by executing them in parallel on multiple cores. Speck provides an infrastructure that allows se...
Edmund B. Nightingale, Daniel Peek, Peter M. Chen,...
ICALP
2009
Springer
14 years 11 months ago
LTL Path Checking Is Efficiently Parallelizable
We present an AC1 (logDCFL) algorithm for checking LTL formulas over finite paths, thus establishing that the problem can be efficiently parallelized. Our construction provides a f...
Lars Kuhtz, Bernd Finkbeiner